Reconfigurable (programmable or writable) semiconductor devices such as FPGAs (field-programmable gate arrays) are widely used due to the flexibility imparted by the rewriting capabilities thereof (Patent Document 1, for example).
Typical island-style FPGAs are constituted by logic elements CLBs (configurable logic blocks), switch elements SBs and CBs, and input/output elements IOBs.
Logic elements CLBs can be programmed to realize a combinatorial circuit, and each of the CLBs is constituted by a data flip-flop (DFF), LUT (lookup table), and the like. A k-input LUT (k-LUT) uses a 2k amount of SRAM (static random access memory) cells to realize a function of k variables. Truth tables of the desired logic functions are held in the SRAM and output is performed by referring to the truth tables in response to input, for example.
In order to generate signal routes between the CLBs, which cause the logic function parts to link to one another, the switch elements CBs and SBs are provided between the CLBs, and these switch elements can switch the signal routes. The switch elements CBs are set between logic blocks LB and wiring channels, and the switch elements SBs perform configuration between vertical and horizontal wiring lines at the intersection points of the wiring lines in the vertical and horizontal directions.
The input/output elements IOBs are configuration elements that serve as an interface between the input/output of the device and the logic elements LBs.
The applicants and inventors of the present invention have developed an “MPLD (memory-based programmable logic device)” (registered trademark) that realizes circuit configurations with memory cell units. Patent Document 1 below, for example, discloses an MPLD. The MPLD is connected to memory arrays called MLUTs (multi-lookup tables). MLUTs store truth table data and are constituted by wiring elements and logic elements. The MLUTs, when arranged in an array and connecting with the MPLD, realize a function that is approximately the same as an FPGA. Furthermore, the MPLD uses the MLUTs as both logic elements and wiring elements via the truth table data, thereby imparting flexibility to the logic regions and wiring regions (Patent Document 2, for example), which differs from an FPGA, which has specialized switching circuits for connection between the memory cell units.